The quest for smaller memory cells to allow increased capacity in integrated circuit memories is a well-known goal. The search for methods of fabricating higher density memories has lead to an entire memory cell, including transistor and storage capacitor, being placed in a single deep cavity (trench) formed in the surface of integrated circuit substrate. See, for example, U.S. Pat. No. 4,830,978, by Teng et al., issued May 16, 1989, which is assigned to the Assignee of the present application and is hereby incorporated by reference.
The inclusion of both the transistor and the capacitor in a single trench has resulted in parasitic capacitance problems. Specifically, the bit line and word line capacitive coupling to the memory cell disrupts the data stored in the memory cell. Moreover, the transistor structure in the trench occupies additional area which creates leakage problems from both the bit line and the storage node, thereby requiring an undesirably large space between memory cells.
A need therefore exists for a dynamic random access memory (DRAM) cell that reduces parasitic capacitance, leakage, and spacing requirements between memory cells.